(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes related to the formation of inductive elements in thin film integrated circuits.
(2) Background of the Invention and Description of Previous Art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. Patterning of the devices elements within the semiconductor surface as well as those lying above the surface such as polysilicon gates and the wiring levels and their via/contact interconnections are accomplished by photolithography. Passive circuit elements such as resistors, capacitors, and inductors are generally patterned over insulative layers deposited on the surface of the semiconductor wafer.
The integration of metal coil inductors into the architecture of integrated circuit chips is relatively recent technology. The benefits of this integration are realized in improved circuit performance as well as a reduction of component space. Not only have metal coil inductors been integrated into monolithic integrated circuit chips, but they have been provided with thin film cores of magnetic and ferromagnetic materials to improve their performance. Among the many problems faced by chip designers who incorporate inductive component on integrated circuit chips is excessive capacitance between the inductor and the substrate. This capacitance greatly reduces the performance of the inductor at high operating frequencies, for example, above1 GHz.
Desaigouder, et.al., U.S. Pat. No. 5,450,263 cites numerous methods for forming inductors in metallization layers over semiconductor integrated circuits. These methods include the suspension of the inductive components over air gaps using bridges with insulative members in order to lower capacitive coupling to the substrate. Abidi, et.al., U.S. Pat. No. 5,539,241 suspends an inductor coil over an air pit formed by anisotropically etching out a portion of the subjacent silicon substrate after the coil is patterned on an insulative layer. Placing a substantial air gap between the inductor and the substrate is an effective way of reducing the capacitance and improving high frequency performance. However, the resultant floating structure is very delicate and can easily be fatally damages during manufacture. Another approach towards the incorporation of a low dielectric constant material between the inductor and the substrate is described by Xie, U.S. Pat. No. 5,736,749. A portion of the silicon substrate beneath the inductive element is selectively made porous by anodic etching of the silicon.
Yu, et.al., U.S. Pat. No. 5,770,509 shows a method for decreasing inductor-to-substrate capacitance by forming a pattern of polysilicon filled trenches in the silicon, running parallel to, and external to the outside of each side of the superjacent inductor metal lines. The polysilicon in the trenches is doped to a conductivity type opposite to that of the substrate. By applying a reverse bias between the polysilicon in the trenches and the substrate, a depletion region is formed between the polysilicon trenches, extending and linking up under the inductor metal. The added series capacitance of the depletion region lowers the overall substrate capacitance. The structure requires extensive additional processing and requires the application of a reverse bias to establish and sustain the depletion region under the inductor coils. Yu's method is difficult and complex and requires reverse biasing. Although it includes only one junction, the method is difficult and complex, requiring the introduction of trench embedded metallization within the silicon and means for bias application. In addition, the design is prone to considerable cross-talk between the inductor and the metallization that provides the junction biasing.
FIG. 1 shows a cross section of an inductor coil 17 formed on an upper level insulative layer of an integrated circuit by conventional means. Specifically, the inductor coil is formed on a second IMD layer 15 and a center connection to the coil 17 is made through a conductive via 16 which connects to a metal stripe 14 on the next subjacent metallization level. The insulative layers which are used in forming integrated circuits elsewhere on the chip, are retained in the inductor region to build up dielectric thickness between the inductor and the silicon substrate 10, thereby lowering the capacitive coupling. In the structure shown in FIG. 1, these comprise a field oxide 11 (FOX), which is formed in the integrated circuit to isolated the semiconductive devices; an ILD (inter level dielectric) layer 12, through which contacts are fabricated to the elements of the semiconductive devices; a first 23 (IMD1) and a second 15 (IMD2) IMD (inter metal dielectric) layer, which insulate between wiring levels in the circuit.
A planar view of the inductor coil is shown in FIG. 2, wherein the cross section of FIG. 1 is designated by the line 1-1'. Although the cumulative thickness of the insulative layers between the inductor coil 17 can be about 0.3 microns or greater, it would be desirable to still further reduce the capacitive coupling of the inductor coil 17 from the substrate 10 with minimal additional process complexity.